The present invention relates to a semiconductor device and, more particularly, to a control circuit for controlling the operation, during power-on, of a power supply circuit which feeds a predetermined power to a plurality of circuit blocks which are all of the same structure, the above-mentioned semiconductor device being used as a synchronous dynamic random access memory (DRAM) which comprises a memory cell array divided into, for example, multi-banks.
FIG. 12 is an equivalent circuit diagram showing an example of the circuit connection between the banks and the precharging power supply circuit in a DRAM which has the conventional multi-bank structure.
In the DRAM shown in FIG. 12, the reference symbols, Bank1 to Bank4, denote banks, the symbol Gen denotes a precharging power supply circuit, the reference numeral 121 denotes a precharging power supply line for feeding a bit line precharging voltage (VBLEQ) to a bit line of each of Bank1 to Bank4, and numeral 122 denotes an earth potential (Vss) line. In this case, one precharging power supply circuit Gen is provided so as to feed a precharging current in common to the precharging power supply line 121.
FIG. 13 is a timing waveform diagram shown for explaining the precharging current feed operation of the precharging power supply circuit Gen shown in FIG. 12.
The precharging power supply circuit Gen feeds its precharging current fully to the respective banks when power is turned on but, during steady-state operation, feeds the precharging current supplementally to the bit lines; and thus, the current (power-on current) fed during power-on is large in amount, and the current fed a predetermined time after the power is turned on can be made relatively small in amount.
However, the operating power of the precharging power supply circuit Gen is the internal power Vint generated within the DRAM chip on the basis of the external power input. As mentioned above, if the precharging current when the power is turned on is large in amount, then the power-on current of the DRAM chip also becomes large in amount.
In case the power-on current of the DRAM chip is large in amount as mentioned above, the following inconvenience is brought about: That is, when power is turned on in a system product using a DRAM, the system power supply may be subjected to a voltage variation for causes such as a voltage drop in the wiring on the system board (mother board), which may in turn cause a malfunction when the system product is started.
Further, it is pointed out that, also in case the precharging power supply circuit Gen is divided into a plurality of precharging power supply circuits, the plurality of precharging power supply circuits simultaneously feed precharge currents, according to the conventional technique, when power is turned on as mentioned above, so that a defect as pointed out above is caused.
Further, in case of a DRAM comprising a multi-bank structure which is constituted in such a manner that the respective banks can be selected independently as, e.g., in case of a synchronous DRAM, the bit lines of the respective banks are connected in common according to the conventional technique, so that, during steady-state operation, the voltage variation caused in the bit line due to, for example, the bit line equalizing operation of a certain bank directly affects the bit lines of other banks (noises are generated due to the interference between the banks), thus adversely affecting the memory cell read operation.
In case of a conventional synchronous DRAM having a multi-bank structure, the following defects are encountered: That is, the power-on current is large in amount, so that a voltage variation is caused in the system power supply when power is turned on in a system product using the DRAM, as a result of which a malfunction is caused when the system product is started. Further, during steady-state operation, noise is apt to be generated due to the interference between the respective banks, which adversely affects the read operation of the memory cells.